A Novel Dynamically Programmable Arithmetic Array (DPAA) Processor for Digital Signal Processing

Tan, Boon-Keat; Yoshimura, Ryuji; Matsuoka, Toshimasa; Taniguchi, Kenji

A Novel Dynamically Programmable Arithmetic Array (DPAA) Processor for Digital Signal Processing

Tan, Boon-Keat; Yoshimura, Ryuji; Matsuoka, Toshimasa et al.

IEICE Transactions on Fundamentals of Electronics, 2001, E84-A(3), 741-747

アクセス数:281件（2025-08-14 18:20 集計）

固定URL: https://hdl.handle.net/11094/51657

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タイトル	A Novel Dynamically Programmable Arithmetic Array (DPAA) Processor for Digital Signal Processing
著者	NRID 1000040114855 1000040114855 著者名 Tan, Boon-Keat
	著者名 Yoshimura, Ryuji
	NRID 1000080324820 1000080324820 ORCID 0000-0003-3876-2679 0000-0003-3876-2679 researchmap permalink read0068628 read0068628 Scopus Author ID 7402741552 7402741552 著者名 Matsuoka, Toshimasa
	NRID 1000020192180 1000020192180 著者名 Taniguchi, Kenji
キーワード等	DPAA
	DSP
	parallel processing
	interconnection topology
	routing flexibility
抄録	A new architecture-based Dynamically Programmable Arithmetic Array processor (DPAA) is proposed for general purpose Digital Signal Processing applications. Parallelism and pipelining are achieved by using DPAA, which consists of various basic arithmetic blocks connected through a code-division multiple access bus interface. The proposed architecture poses 100% interconnection flexibility because connections are done virtually through code matching instead of physical wire connections. Compared to conventional multiplexing architectures, the proposed interconnection topology consumes less chip area and thus, more arithmetic blocks can be incorporated. A 16-bit prototype chip incorporating 10 multipliers and 40 other arithmetic blocks had been implemented into a 4.5 mm × 4.5 mm chip with 0.6 µm CMOS process. DPAA also features its simple programmability, as numerical formula can be used to configure the processor without programming languages or specialized CAD tools.
出版者	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
収録物名	IEICE Transactions on Fundamentals of Electronics
巻(号)	E84-A(3)
ページ	741-747
刊行年月	2001-03
言語	英語
ハンドルURL	https://hdl.handle.net/11094/51657
PISSN	09168508
NCID	AA10826239
関連情報 (references)	URI https://search.ieice.org/
アクセス権	open access
権利情報	copyright©2001 IEICE
出版タイプ	Version of Record
カテゴリ	学術雑誌論文 Journal Article

資源タイプ	学術雑誌論文
ローカル資源タイプ	学術雑誌論文
DCMI資源タイプ	text
DCTERMS.bibliographicCitation	IEICE Transactions on Fundamentals of Electronics. 2001, E84-A(3), p. 741-747
DC.title	A Novel Dynamically Programmable Arithmetic Array (DPAA) Processor for Digital Signal Processing
DC.creator	Tan, Boon-Keat
	Yoshimura, Ryuji
	Matsuoka, Toshimasa
	Taniguchi, Kenji
DC.publisher	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
DC.language' scheme='DCTERMS.RFC1766	英語
DC.type' scheme='DCTERMS.DCMIType	text
DCTERMS.issued' scheme='DCTERMS.W3CDTF	2001-03
DC.relation' scheme='DCTERMS.URI	https://search.ieice.org/
DC.subject	DPAA
	DSP
	parallel processing
	interconnection topology
	routing flexibility
DCTERMS.abstract	A new architecture-based Dynamically Programmable Arithmetic Array processor (DPAA) is proposed for general purpose Digital Signal Processing applications. Parallelism and pipelining are achieved by using DPAA, which consists of various basic arithmetic blocks connected through a code-division multiple access bus interface. The proposed architecture poses 100% interconnection flexibility because connections are done virtually through code matching instead of physical wire connections. Compared to conventional multiplexing architectures, the proposed interconnection topology consumes less chip area and thus, more arithmetic blocks can be incorporated. A 16-bit prototype chip incorporating 10 multipliers and 40 other arithmetic blocks had been implemented into a 4.5 mm × 4.5 mm chip with 0.6 µm CMOS process. DPAA also features its simple programmability, as numerical formula can be used to configure the processor without programming languages or specialized CAD tools.
DC.rights	copyright©2001 IEICE
DC.format	51657
citation_title	A Novel Dynamically Programmable Arithmetic Array (DPAA) Processor for Digital Signal Processing
citation_author	Tan, Boon-Keat
	Yoshimura, Ryuji
	Matsuoka, Toshimasa
	Taniguchi, Kenji
citation_publisher	電子情報通信学会
citation_language	英語
citation_date	2001-03
citation_journal_title	IEICE Transactions on Fundamentals of Electronics
citation_volume	E84-A
citation_issue	3
citation_firstpage	741
citation_lastpage	747
citation_public_url	https://hdl.handle.net/11094/51657
citation_abstract_html_url	https://search.ieice.org/

A Novel Dynamically Programmable Arithmetic Array (DPAA) Processor for Digital Signal Processing

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