Dynamically Programmable Parallel Processor (DPPP) : A Novel Reconfigurable Architecture with Simple Program Interface

Tan, Boon-Keat; Yoshimura, Ryuji; Matsuoka, Toshimasa; Taniguchi, Kenji

Dynamically Programmable Parallel Processor (DPPP) : A Novel Reconfigurable Architecture with Simple Program Interface

Tan, Boon-Keat; Yoshimura, Ryuji; Matsuoka, Toshimasa et al.

IEICE Transactions on Information and Systems, 2001, E84-D(11), 1521-1527

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固定URL: https://hdl.handle.net/11094/51672

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タイトル	Dynamically Programmable Parallel Processor (DPPP) : A Novel Reconfigurable Architecture with Simple Program Interface
著者	NRID 1000040114855 1000040114855 著者名 Tan, Boon-Keat
	著者名 Yoshimura, Ryuji
	NRID 1000080324820 1000080324820 ORCID 0000-0003-3876-2679 0000-0003-3876-2679 researchmap permalink read0068628 read0068628 Scopus Author ID 7402741552 7402741552 著者名 Matsuoka, Toshimasa
	NRID 1000020192180 1000020192180 著者名 Taniguchi, Kenji
キーワード等	CDMA bus
	parallel processing
	interconnection topology
	routing flexibility
	fault tolerant
抄録	This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm × 4.5 mm chip using 0.6 µm CMOS process.
出版者	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
収録物名	IEICE Transactions on Information and Systems
巻(号)	E84-D(11)
ページ	1521-1527
刊行年月	2001-11
言語	英語
ハンドルURL	https://hdl.handle.net/11094/51672
PISSN	09168532
NCID	AA10826272
関連情報 (references)	URI https://search.ieice.org/
アクセス権	open access
権利情報	copyright©2001 IEICE
出版タイプ	Version of Record
カテゴリ	学術雑誌論文 Journal Article

資源タイプ	学術雑誌論文
ローカル資源タイプ	学術雑誌論文
DCMI資源タイプ	text
DCTERMS.bibliographicCitation	IEICE Transactions on Information and Systems. 2001, E84-D(11), p. 1521-1527
DC.title	Dynamically Programmable Parallel Processor (DPPP) : A Novel Reconfigurable Architecture with Simple Program Interface
DC.creator	Tan, Boon-Keat
	Yoshimura, Ryuji
	Matsuoka, Toshimasa
	Taniguchi, Kenji
DC.publisher	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
DC.language' scheme='DCTERMS.RFC1766	英語
DC.type' scheme='DCTERMS.DCMIType	text
DCTERMS.issued' scheme='DCTERMS.W3CDTF	2001-11
DC.relation' scheme='DCTERMS.URI	https://search.ieice.org/
DC.subject	CDMA bus
	parallel processing
	interconnection topology
	routing flexibility
	fault tolerant
DCTERMS.abstract	This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm × 4.5 mm chip using 0.6 µm CMOS process.
DC.rights	copyright©2001 IEICE
DC.format	51672
citation_title	Dynamically Programmable Parallel Processor (DPPP) : A Novel Reconfigurable Architecture with Simple Program Interface
citation_author	Tan, Boon-Keat
	Yoshimura, Ryuji
	Matsuoka, Toshimasa
	Taniguchi, Kenji
citation_publisher	電子情報通信学会
citation_language	英語
citation_date	2001-11
citation_journal_title	IEICE Transactions on Information and Systems
citation_volume	E84-D
citation_issue	11
citation_firstpage	1521
citation_lastpage	1527
citation_public_url	https://hdl.handle.net/11094/51672
citation_abstract_html_url	https://search.ieice.org/

Dynamically Programmable Parallel Processor (DPPP) : A Novel Reconfigurable Architecture with Simple Program Interface

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