High Speed and Noise Tolerant Parallel Bus Interface for VLSI Systems Using Multi Bit Code Division Multiple Access

Shimizu, Shinsaku; Matsuoka, Toshimasa; Taniguchi, Kenji

High Speed and Noise Tolerant Parallel Bus Interface for VLSI Systems Using Multi Bit Code Division Multiple Access

Shimizu, Shinsaku; Matsuoka, Toshimasa; Taniguchi, Kenji

IEICE Transactions on Electronics, 2004, E87-C(11), 1923-1927

アクセス数:317件（2025-08-15 06:48 集計）

固定URL: https://hdl.handle.net/11094/51684

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タイトル	High Speed and Noise Tolerant Parallel Bus Interface for VLSI Systems Using Multi Bit Code Division Multiple Access
著者	著者名 Shimizu, Shinsaku
	NRID 1000080324820 1000080324820 ORCID 0000-0003-3876-2679 0000-0003-3876-2679 researchmap permalink read0068628 read0068628 Scopus Author ID 7402741552 7402741552 著者名 Matsuoka, Toshimasa
	NRID 1000020192180 1000020192180 著者名 Taniguchi, Kenji
キーワード等	parallel-CDMA interface
	noise tolerance
	multi-bit transmission
抄録	An efficient data transmission interface for VLSI systems, Multi-Bit Parallel Code Division Multiple Access (MB/P-CDMA) interface, has been designed with 0.35 µm CMOS technology. The proposed interface achieves 1.12 Gb/s data rate (80 MHz, 8 bit bus) using multi-bit transmission at each clock per transmitter. The proposed CDMA interface ensures higher speed operation than conventional interface even in noisy environments. Each of the transmitters and receivers occupies the die area of 290 × 360 µm2 and 240 × 280 µm2, respectively.
出版者	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
収録物名	IEICE Transactions on Electronics
巻(号)	E87-C(11)
ページ	1923-1927
刊行年月	2004-11
言語	英語
ハンドルURL	https://hdl.handle.net/11094/51684
PISSN	09168516
NCID	AA10826261
関連情報 (references)	URI https://search.ieice.org/
アクセス権	open access
権利情報	copyright©2004 IEICE
出版タイプ	Version of Record
カテゴリ	学術雑誌論文 Journal Article

資源タイプ	学術雑誌論文
ローカル資源タイプ	学術雑誌論文
DCMI資源タイプ	text
DCTERMS.bibliographicCitation	IEICE Transactions on Electronics. 2004, E87-C(11), p. 1923-1927
DC.title	High Speed and Noise Tolerant Parallel Bus Interface for VLSI Systems Using Multi Bit Code Division Multiple Access
DC.creator	Shimizu, Shinsaku
	Matsuoka, Toshimasa
	Taniguchi, Kenji
DC.publisher	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
DC.language' scheme='DCTERMS.RFC1766	英語
DC.type' scheme='DCTERMS.DCMIType	text
DCTERMS.issued' scheme='DCTERMS.W3CDTF	2004-11
DC.relation' scheme='DCTERMS.URI	https://search.ieice.org/
DC.subject	parallel-CDMA interface
	noise tolerance
	multi-bit transmission
DCTERMS.abstract	An efficient data transmission interface for VLSI systems, Multi-Bit Parallel Code Division Multiple Access (MB/P-CDMA) interface, has been designed with 0.35 µm CMOS technology. The proposed interface achieves 1.12 Gb/s data rate (80 MHz, 8 bit bus) using multi-bit transmission at each clock per transmitter. The proposed CDMA interface ensures higher speed operation than conventional interface even in noisy environments. Each of the transmitters and receivers occupies the die area of 290 × 360 µm2 and 240 × 280 µm2, respectively.
DC.rights	copyright©2004 IEICE
DC.format	51684
citation_title	High Speed and Noise Tolerant Parallel Bus Interface for VLSI Systems Using Multi Bit Code Division Multiple Access
citation_author	Shimizu, Shinsaku
	Matsuoka, Toshimasa
	Taniguchi, Kenji
citation_publisher	電子情報通信学会
citation_language	英語
citation_date	2004-11
citation_journal_title	IEICE Transactions on Electronics
citation_volume	E87-C
citation_issue	11
citation_firstpage	1923
citation_lastpage	1927
citation_public_url	https://hdl.handle.net/11094/51684
citation_abstract_html_url	https://search.ieice.org/

High Speed and Noise Tolerant Parallel Bus Interface for VLSI Systems Using Multi Bit Code Division Multiple Access

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