Analytical Expression Based Design of a Low-Voltage FD-SOI CMOS Low-Noise Amplifier

Kihara, Takao; Kim, Guechol; Goto, Masaru; Nakamura, Keiji; Shimizu, Yoshiyuki; Matsuoka, Toshimasa; Taniguchi, Kenji

doi:https://doi.org/10.1093/ietfec/e90-a.2.317

Analytical Expression Based Design of a Low-Voltage FD-SOI CMOS Low-Noise Amplifier

Kihara, Takao; Kim, Guechol; Goto, Masaru et al.

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, 2007, E90-A(2), 317-325

アクセス数:1,219件（2025-08-15 07:41 集計）

固定URL: https://hdl.handle.net/11094/51688

閲覧可能ファイル

ファイル	フォーマット	利用条件	サイズ	閲覧回数	利用開始日	説明	information
IEICE TRANSACTIONS_E90-A_2_317	pdf	なし	796 KB	351	2015.05.28

論文情報

ファイル出力 EndNote Basic出力 Mendeley出力

タイトル	Analytical Expression Based Design of a Low-Voltage FD-SOI CMOS Low-Noise Amplifier
著者	著者名 Kihara, Takao
	著者名 Kim, Guechol
	著者名 Goto, Masaru
	NRID 1000020227888 1000020227888 著者名 Nakamura, Keiji
	著者名 Shimizu, Yoshiyuki
	NRID 1000080324820 1000080324820 ORCID 0000-0003-3876-2679 0000-0003-3876-2679 researchmap permalink read0068628 read0068628 Scopus Author ID 7402741552 7402741552 著者名 Matsuoka, Toshimasa
	NRID 1000020192180 1000020192180 著者名 Taniguchi, Kenji
キーワード等	low-noise amplifier (LNA)
	FD-SOI CMOS
	noise
	linearity
	low-voltage
抄録	We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-µm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Measurement results show a power gain of 23 dB, NF of 1.7 dB and IIP3 of -6.1 dBm with a power consumption of 8.3 mW. These measured results are consistent with calculated results, which ensures the validity of the derived equations and the proposed design methodology.
出版者	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
収録物名	IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
巻(号)	E90-A(2)
ページ	317-325
刊行年月	2007-02
言語	英語
ハンドルURL	https://hdl.handle.net/11094/51688
PISSN	09168508
eISSN	17451337
NCID	AA10826239
関連情報 (isIdenticalTo)	DOI (出版社版) https://doi.org/10.1093/ietfec/e90-a.2.317
アクセス権	open access
権利情報	copyright©2007 IEICE
出版タイプ	Version of Record
カテゴリ	学術雑誌論文 Journal Article

資源タイプ	学術雑誌論文
ローカル資源タイプ	学術雑誌論文
DCMI資源タイプ	text
DCTERMS.bibliographicCitation	IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences. 2007, E90-A(2), p. 317-325
DC.title	Analytical Expression Based Design of a Low-Voltage FD-SOI CMOS Low-Noise Amplifier
DC.creator	Kihara, Takao
	Kim, Guechol
	Goto, Masaru
	Nakamura, Keiji
	Shimizu, Yoshiyuki
	Matsuoka, Toshimasa
	Taniguchi, Kenji
DC.publisher	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
DC.language' scheme='DCTERMS.RFC1766	英語
DC.type' scheme='DCTERMS.DCMIType	text
DCTERMS.issued' scheme='DCTERMS.W3CDTF	2007-02
DC.identifier	https://doi.org/10.1093/ietfec/e90-a.2.317
DC.subject	low-noise amplifier (LNA)
	FD-SOI CMOS
	noise
	linearity
	low-voltage
DCTERMS.abstract	We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-µm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Measurement results show a power gain of 23 dB, NF of 1.7 dB and IIP3 of -6.1 dBm with a power consumption of 8.3 mW. These measured results are consistent with calculated results, which ensures the validity of the derived equations and the proposed design methodology.
DC.rights	copyright©2007 IEICE
DC.format	51688
citation_title	Analytical Expression Based Design of a Low-Voltage FD-SOI CMOS Low-Noise Amplifier
citation_author	Kihara, Takao
	Kim, Guechol
	Goto, Masaru
	Nakamura, Keiji
	Shimizu, Yoshiyuki
	Matsuoka, Toshimasa
	Taniguchi, Kenji
citation_publisher	電子情報通信学会
citation_language	英語
citation_date	2007-02
citation_journal_title	IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
citation_volume	E90-A
citation_issue	2
citation_firstpage	317
citation_lastpage	325
citation_doi	https://doi.org/10.1093/ietfec/e90-a.2.317
citation_public_url	https://hdl.handle.net/11094/51688

Analytical Expression Based Design of a Low-Voltage FD-SOI CMOS Low-Noise Amplifier

閲覧可能ファイル

論文情報

論文詳細を表示