A CMOS LOW-DROPOUT REGULATOR WITH A DYNAMIC-BIASED GAIN STAGE

Wang, Honglai; Dai, Yujie; Zhang, Xiaoxing et al.

Far East Journal of Electronics and Communications, 2012, 7(2), 67-81

アクセス数:391件（2025-08-14 21:08 集計）

固定URL: https://hdl.handle.net/11094/51735

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タイトル
A CMOS LOW-DROPOUT REGULATOR WITH A DYNAMIC-BIASED GAIN STAGE
著者
著者名
Wang, Honglai
著者名
Dai, Yujie
著者名
Zhang, Xiaoxing
著者名
Lv, Yingjie
NRID
1000080324820 1000080324820
ORCID
0000-0003-3876-2679 0000-0003-3876-2679
researchmap permalink
read0068628 read0068628
Scopus Author ID
7402741552 7402741552
著者名
Matsuoka, Toshimasa
NRID
1000030543532 1000030543532
著者名
Wang, Jun
NRID
1000020192180 1000020192180
著者名
Taniguchi, Kenji
キーワード等
CMOS
frequency compensation
low-dropout(LDO) regulator
dynamic-biased gain stage
抄録
This paper presents a CMOS low-dropout (LDO) regulation with a dynamic-biased gain stage. The dynamic-biased gain stage which has the dynamic adjustable output resistance, current and gain is designed as a second stage driving the power transistor. A LDO regulator with the proposed gain stage has been implemented in a 0.18mm standard CMOS process and occupies 0.11mm2 chip area. The experimental results show that the proposed LDO regulator can be stable without any additional on-chip compensation capacitors or complex circuit. The LDO regulator provides a full load transient response of settling time less than 15ms with a 2.2mF load capacitor and the voltage variation is less than 40mV. Furthermore, the load regulation and line regulation are 321mV/mA and 1.8mV/V, respectively.
出版者
Pushpa Publishing House
収録物名
Far East Journal of Electronics and Communications
巻(号)
7(2)
ページ
67-81
刊行年月
2012-04
言語
英語
ハンドルURL
https://hdl.handle.net/11094/51735
PISSN
09737006
アクセス権
open access
権利情報
© 2011 Pushpa Publishing House
出版タイプ
Version of Record
カテゴリ
学術雑誌論文 Journal Article