A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION

Cui, Ji; Tani, Sadahiro; Ohara, Kenji; Hirai, Yusaku; Matsuoka, Toshimasa

doi:https://doi.org/10.17654/fjecjun2015_105_115

A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION

Cui, Ji; Tani, Sadahiro; Ohara, Kenji et al.

Far East Journal of Electronics and Communications, 2015, 14(2), 105-115

アクセス数:774件（2025-09-28 16:36 集計）

固定URL: https://hdl.handle.net/11094/51765

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FEJEC14_2_105	pdf	なし	395 KB	1,116	2015.06.24	出版社版/publisher

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タイトル	A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION
著者	著者名 Cui, Ji
	著者名 Tani, Sadahiro
	著者名 Ohara, Kenji
	著者名 Hirai, Yusaku
	NRID 1000080324820 1000080324820 ORCID 0000-0003-3876-2679 0000-0003-3876-2679 researchmap permalink read0068628 read0068628 Scopus Author ID 7402741552 7402741552 著者名 Matsuoka, Toshimasa
キーワード等	dynamic latched comparator
キーワード等	offset voltage cancellation
抄録	This paper presents a novel dynamic latched comparator that uses a built-in offset-cancellation technique. The proposed offset-cancellation scheme does not require any extra amplifiers or digital-assistant cancellation. Combining a conventional dynamic latched comparator with a one-stage amplifier benefits from not only an enhancement in comparator gain but also a reduction in power consumption. The Monte-Carlo simulation results, which were derived by using a 130‑nm CMOS process, show that the comparator achieved a 3.8 mV equivalent input-referred offset voltage at a 10 MHz clock rate while dissipating 2.7 μW from a 1.2V supply.
出版者	Pushpa Publishing House
収録物名	Far East Journal of Electronics and Communications
巻(号)	14(2)
ページ	105-115
刊行年月	2015-06
言語	英語
ハンドルURL	https://hdl.handle.net/11094/51765
PISSN	09737006
関連情報 (isIdenticalTo)	DOI (出版社版) https://doi.org/10.17654/fjecjun2015_105_115
アクセス権	open access
権利情報	© 2015 Pushpa Publishing House
出版タイプ	Version of Record
カテゴリ	学術雑誌論文 Journal Article

資源タイプ	学術雑誌論文
ローカル資源タイプ	学術雑誌論文
DCMI資源タイプ	text
DCTERMS.bibliographicCitation	Far East Journal of Electronics and Communications. 2015, 14(2), p. 105-115
DC.title	A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION
DC.creator	Cui, Ji
	Tani, Sadahiro
	Ohara, Kenji
	Hirai, Yusaku
	Matsuoka, Toshimasa
DC.publisher	Pushpa Publishing House
DC.language' scheme='DCTERMS.RFC1766	英語
DC.type' scheme='DCTERMS.DCMIType	text
DCTERMS.issued' scheme='DCTERMS.W3CDTF	2015-06
DC.identifier	https://doi.org/10.17654/fjecjun2015_105_115
DC.subject	dynamic latched comparator
DC.subject	offset voltage cancellation
DCTERMS.abstract	This paper presents a novel dynamic latched comparator that uses a built-in offset-cancellation technique. The proposed offset-cancellation scheme does not require any extra amplifiers or digital-assistant cancellation. Combining a conventional dynamic latched comparator with a one-stage amplifier benefits from not only an enhancement in comparator gain but also a reduction in power consumption. The Monte-Carlo simulation results, which were derived by using a 130‑nm CMOS process, show that the comparator achieved a 3.8 mV equivalent input-referred offset voltage at a 10 MHz clock rate while dissipating 2.7 μW from a 1.2V supply.
DC.rights	© 2015 Pushpa Publishing House
DC.format	51765
citation_title	A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION
citation_author	Cui, Ji
	Tani, Sadahiro
	Ohara, Kenji
	Hirai, Yusaku
	Matsuoka, Toshimasa
citation_publisher	Pushpa Publishing House
citation_language	英語
citation_date	2015-06
citation_journal_title	Far East Journal of Electronics and Communications
citation_volume	14
citation_issue	2
citation_firstpage	105
citation_lastpage	115
citation_doi	https://doi.org/10.17654/fjecjun2015_105_115
citation_public_url	https://hdl.handle.net/11094/51765

A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION

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