ANALYSIS OF A CONTROLLER-BASED ALL-DIGITAL PHASE-LOCKED LOOP

Radhapuram, Saichandrateja; Bae, Jungnam; Jo, Ikkyun; Wang, Weimin; Matsuoka, Toshimasa

doi:https://doi.org/10.17654/fjecsep2015_057_073

ANALYSIS OF A CONTROLLER-BASED ALL-DIGITAL PHASE-LOCKED LOOP

Radhapuram, Saichandrateja; Bae, Jungnam; Jo, Ikkyun et al.

Far East Journal of Electronics and Communications, 2015, 15(1), 57-73

アクセス数:905件（2025-09-28 12:36 集計）

固定URL: https://hdl.handle.net/11094/52099

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ファイル	フォーマット	利用条件	サイズ	閲覧回数	利用開始日	説明	information
Far East J_1410719227	pdf	なし	406 KB	820	2015.08.03	出版社版/publisher
Errata_Far East J_1410719227	pdf	なし	110 KB	141	2017.11.24	正誤表/Errata

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タイトル	ANALYSIS OF A CONTROLLER-BASED ALL-DIGITAL PHASE-LOCKED LOOP
著者	著者名 Radhapuram, Saichandrateja
	著者名 Bae, Jungnam
	著者名 Jo, Ikkyun
	著者名 Wang, Weimin
	NRID 1000080324820 1000080324820 ORCID 0000-0003-3876-2679 0000-0003-3876-2679 researchmap permalink read0068628 read0068628 Scopus Author ID 7402741552 7402741552 著者名 Matsuoka, Toshimasa
キーワード等	all-digital phase-locked loop
	phase interpolator
	z-domain
	s-domain
	steady-state error
抄録	A design procedure of an all-digital phase-locked loop (ADPLL) based on phase selection mechanism with loop stability independent of process, supply voltage and temperature is presented. A poly-phase filter and a phase interpolator are used to generate multiple phases to reduce the phase error. The modeling of proposed ADPLL structure is extensively investigated and mathematically described. For a phase and a frequency step input change, the closed-loop system of the proposed ADPLL eliminates phase error. Time-domain response of the behavioral-level simulation of the proposed structure on 130-nm CMOS technology with 0.7V supply voltage reveals the presented analytical model.
出版者	Pushpa Publishing House
収録物名	Far East Journal of Electronics and Communications
巻(号)	15(1)
ページ	57-73
刊行年月	2015-09
言語	英語
ハンドルURL	https://hdl.handle.net/11094/52099
PISSN	09737006
関連情報 (isIdenticalTo)	DOI (出版社版) https://doi.org/10.17654/fjecsep2015_057_073
アクセス権	open access
権利情報	© 2015 Pushpa Publishing House
出版タイプ	Version of Record
カテゴリ	学術雑誌論文 Journal Article

資源タイプ	学術雑誌論文
ローカル資源タイプ	学術雑誌論文
DCMI資源タイプ	text
DCTERMS.bibliographicCitation	Far East Journal of Electronics and Communications. 2015, 15(1), p. 57-73
DC.title	ANALYSIS OF A CONTROLLER-BASED ALL-DIGITAL PHASE-LOCKED LOOP
DC.creator	Radhapuram, Saichandrateja
	Bae, Jungnam
	Jo, Ikkyun
	Wang, Weimin
	Matsuoka, Toshimasa
DC.publisher	Pushpa Publishing House
DC.language' scheme='DCTERMS.RFC1766	英語
DC.type' scheme='DCTERMS.DCMIType	text
DCTERMS.issued' scheme='DCTERMS.W3CDTF	2015-09
DC.identifier	https://doi.org/10.17654/fjecsep2015_057_073
DC.subject	all-digital phase-locked loop
	phase interpolator
	z-domain
	s-domain
	steady-state error
DCTERMS.abstract	A design procedure of an all-digital phase-locked loop (ADPLL) based on phase selection mechanism with loop stability independent of process, supply voltage and temperature is presented. A poly-phase filter and a phase interpolator are used to generate multiple phases to reduce the phase error. The modeling of proposed ADPLL structure is extensively investigated and mathematically described. For a phase and a frequency step input change, the closed-loop system of the proposed ADPLL eliminates phase error. Time-domain response of the behavioral-level simulation of the proposed structure on 130-nm CMOS technology with 0.7V supply voltage reveals the presented analytical model.
DC.rights	© 2015 Pushpa Publishing House
DC.format	52099
citation_title	ANALYSIS OF A CONTROLLER-BASED ALL-DIGITAL PHASE-LOCKED LOOP
citation_author	Radhapuram, Saichandrateja
	Bae, Jungnam
	Jo, Ikkyun
	Wang, Weimin
	Matsuoka, Toshimasa
citation_publisher	Pushpa Publishing House
citation_language	英語
citation_date	2015-09
citation_journal_title	Far East Journal of Electronics and Communications
citation_volume	15
citation_issue	1
citation_firstpage	57
citation_lastpage	73
citation_doi	https://doi.org/10.17654/fjecsep2015_057_073
citation_public_url	https://hdl.handle.net/11094/52099

ANALYSIS OF A CONTROLLER-BASED ALL-DIGITAL PHASE-LOCKED LOOP

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