A low-power CMOS programmable frequency divider with novel retiming scheme

Radhapuram, Saichandrateja; Bae, Jungnam; Jo, Ikkyun; Kihara, Takao; Matsuoka, Toshimasa

doi:https://doi.org/10.1587/elex.12.20141233

アクセス数:314件（2024-06-17 17:21 集計）

固定URL: https://hdl.handle.net/11094/51718

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IEICE Electronics Express12_6_20141233	pdf	なし	2.53 MB	254	2015.05.28

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タイトル	A low-power CMOS programmable frequency divider with novel retiming scheme
著者	著者名 Radhapuram, Saichandrateja
	著者名 Bae, Jungnam
	著者名 Jo, Ikkyun
	著者名 Kihara, Takao
	NRID 1000080324820 1000080324820 ORCID 0000-0003-3876-2679 0000-0003-3876-2679 researchmap permalink read0068628 read0068628 Scopus Author ID 7402741552 7402741552 著者名 Matsuoka, Toshimasa
キーワード等	pulse-swallow
	retiming
	SR latch
	modulus control
	CMOS
抄録	We propose a novel pulse-swallow programmable frequency divider with a D flip-flop for retiming. The proposed scheme reduces the critical delay path of the modulus control (MC) signal extending the MC timing margin. This enables the high-speed operation of the divider. Moreover, unlike the conventional retiming structure, the MC signal is set and reset by a single signal triggered reset circuitry to eliminate the unwanted division ratio offset and the possible malfunction of set-reset (SR) latch. Simulation results show that the proposed divider designed in 130-nm CMOS technology consumes 53 µW at 1-GHz operation frequency from a 0.7-V supply voltage. The proposed divider achieves the lowest power consumption among the previously reported dividers at GHz operations.
出版者	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
収録物名	IEICE Electronics Express
巻(号)	12(6)
ページ	20141233
刊行年月	2015-03
言語	英語
ハンドルURL	https://hdl.handle.net/11094/51718
eISSN	13492543
関連情報 (isIdenticalTo)	DOI (出版社版) https://doi.org/10.1587/elex.12.20141233
アクセス権	open access
権利情報	copyright©2015 IEICE
出版タイプ	Version of Record
カテゴリ	学術雑誌論文 Journal Article

資源タイプ	学術雑誌論文
ローカル資源タイプ	学術雑誌論文
DCMI資源タイプ	text
DCTERMS.bibliographicCitation	IEICE Electronics Express. 2015, 12(6), p. 20141233
DC.title	A low-power CMOS programmable frequency divider with novel retiming scheme
DC.creator	Radhapuram, Saichandrateja
	Bae, Jungnam
	Jo, Ikkyun
	Kihara, Takao
	Matsuoka, Toshimasa
DC.publisher	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
DC.language' scheme='DCTERMS.RFC1766	英語
DC.type' scheme='DCTERMS.DCMIType	text
DCTERMS.issued' scheme='DCTERMS.W3CDTF	2015-03
DC.identifier	https://doi.org/10.1587/elex.12.20141233
DC.subject	pulse-swallow
	retiming
	SR latch
	modulus control
	CMOS
DCTERMS.abstract	We propose a novel pulse-swallow programmable frequency divider with a D flip-flop for retiming. The proposed scheme reduces the critical delay path of the modulus control (MC) signal extending the MC timing margin. This enables the high-speed operation of the divider. Moreover, unlike the conventional retiming structure, the MC signal is set and reset by a single signal triggered reset circuitry to eliminate the unwanted division ratio offset and the possible malfunction of set-reset (SR) latch. Simulation results show that the proposed divider designed in 130-nm CMOS technology consumes 53 µW at 1-GHz operation frequency from a 0.7-V supply voltage. The proposed divider achieves the lowest power consumption among the previously reported dividers at GHz operations.
DC.rights	copyright©2015 IEICE
DC.format	51718
citation_title	A low-power CMOS programmable frequency divider with novel retiming scheme
citation_author	Radhapuram, Saichandrateja
	Bae, Jungnam
	Jo, Ikkyun
	Kihara, Takao
	Matsuoka, Toshimasa
citation_publisher	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
citation_language	英語
citation_date	2015-03
citation_journal_title	IEICE Electronics Express
citation_volume	12
citation_issue	6
citation_firstpage	20141233
citation_doi	https://doi.org/10.1587/elex.12.20141233
citation_public_url	https://hdl.handle.net/11094/51718

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