A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices

Bae, Jungnam; Radhapuram, Saichandrateja; Jo, Ikkyun; Wang, Weimin; Kihara, Takao; Matsuoka, Toshimasa

doi:https://doi.org/10.1587/transele.e99.c.431

A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices

Bae, Jungnam; Radhapuram, Saichandrateja; Jo, Ikkyun et al.

IEICE TRANSACTIONS on Electronics, 2016, 99-C(4), 431-439

アクセス数:948件（2025-07-12 20:22 集計）

固定URL: https://hdl.handle.net/11094/55420

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タイトル	A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices
著者	著者名 Bae, Jungnam
	著者名 Radhapuram, Saichandrateja
	著者名 Jo, Ikkyun
	著者名 Wang, Weimin
	著者名 Kihara, Takao
	NRID 1000080324820 1000080324820 ORCID 0000-0003-3876-2679 0000-0003-3876-2679 researchmap permalink read0068628 read0068628 Scopus Author ID 7402741552 7402741552 著者名 Matsuoka, Toshimasa
キーワード等	all-digital phase-locked loop
	controller
	digitally-controlled oscillator
	phase interpolator
	CMOS
	MICS
抄録	A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band was designed in this study. In the proposed design, controller-based loop topology is used to control the phase and frequency to ensure the reliable handling of the ADPLL output signal. A digitally-controlled oscillator with a delta-sigma modulator was employed to achieve high frequency resolution. The phase error was reduced by a phase selector with a 64-phase signal from the phase interpolator. Fabricated using a 130-nm CMOS process, the ADPLL has an active area of 0.64 mm^2, consumes 840 µW from a 0.7-V supply voltage, and has a settling time of 80 µs. The phase noise was measured to be -114 dBc/Hz at an offset frequency of 200 kHz.
出版者	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
収録物名	IEICE TRANSACTIONS on Electronics
巻(号)	99-C(4)
ページ	431-439
刊行年月	2016-04-01
言語	英語
ハンドルURL	https://hdl.handle.net/11094/55420
PISSN	09168524
eISSN	17451353
関連情報 (isIdenticalTo)	DOI (出版社版) https://doi.org/10.1587/transele.e99.c.431
アクセス権	open access
権利情報	Copyright © 2016 by The Institute of Electronics, Information and Communication Engineers
出版タイプ	Version of Record
カテゴリ	学術雑誌論文 Journal Article

資源タイプ	学術雑誌論文
ローカル資源タイプ	学術雑誌論文
DCMI資源タイプ	text
DCTERMS.bibliographicCitation	IEICE TRANSACTIONS on Electronics. 2016, 99-C(4), p. 431-439
DC.title	A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices
DC.creator	Bae, Jungnam
	Radhapuram, Saichandrateja
	Jo, Ikkyun
	Wang, Weimin
	Kihara, Takao
	Matsuoka, Toshimasa
DC.publisher	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
DC.language' scheme='DCTERMS.RFC1766	英語
DC.type' scheme='DCTERMS.DCMIType	text
DCTERMS.issued' scheme='DCTERMS.W3CDTF	2016-04-01
DC.identifier	https://doi.org/10.1587/transele.e99.c.431
DC.subject	all-digital phase-locked loop
	controller
	digitally-controlled oscillator
	phase interpolator
	CMOS
	MICS
DCTERMS.abstract	A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band was designed in this study. In the proposed design, controller-based loop topology is used to control the phase and frequency to ensure the reliable handling of the ADPLL output signal. A digitally-controlled oscillator with a delta-sigma modulator was employed to achieve high frequency resolution. The phase error was reduced by a phase selector with a 64-phase signal from the phase interpolator. Fabricated using a 130-nm CMOS process, the ADPLL has an active area of 0.64 mm^2, consumes 840 µW from a 0.7-V supply voltage, and has a settling time of 80 µs. The phase noise was measured to be -114 dBc/Hz at an offset frequency of 200 kHz.
DC.rights	Copyright © 2016 by The Institute of Electronics, Information and Communication Engineers
DC.format	55420
citation_title	A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices
citation_author	Bae, Jungnam
	Radhapuram, Saichandrateja
	Jo, Ikkyun
	Wang, Weimin
	Kihara, Takao
	Matsuoka, Toshimasa
citation_publisher	電子情報通信学会
citation_language	英語
citation_date	2016-04-01
citation_journal_title	IEICE TRANSACTIONS on Electronics
citation_volume	99-C
citation_issue	4
citation_firstpage	431
citation_lastpage	439
citation_doi	https://doi.org/10.1587/transele.e99.c.431
citation_public_url	https://hdl.handle.net/11094/55420

A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices

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