A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices

Bae, Jungnam; Radhapuram, Saichandrateja; Jo, Ikkyun; Wang, Weimin; Kihara, Takao; Matsuoka, Toshimasa

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論文情報

タイトル	A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices
著者	Bae, Jungnam Bae, Jungnam
	Radhapuram, Saichandrateja Radhapuram, Saichandrateja
	Jo, Ikkyun Jo, Ikkyun
	Wang, Weimin Wang, Weimin
	Kihara, Takao Kihara, Takao
	Matsuoka, Toshimasa Matsuoka, Toshimasa
キーワード等	all-digital phase-locked loop
	controller
	digitally-controlled oscillator
	phase interpolator
	CMOS
	MICS
抄録	A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band was designed in this study. In the proposed design, controller-based loop topology is used to control the phase and frequency to ensure the reliable handling of the ADPLL output signal. A digitally-controlled oscillator with a delta-sigma modulator was employed to achieve high frequency resolution. The phase error was reduced by a phase selector with a 64-phase signal from the phase interpolator. Fabricated using a 130-nm CMOS process, the ADPLL has an active area of 0.64 mm^2, consumes 840 µW from a 0.7-V supply voltage, and has a settling time of 80 µs. The phase noise was measured to be -114 dBc/Hz at an offset frequency of 200 kHz.
公開者	電子情報通信学会
公開者の別表記	The Institute of Electronics, Information and Communication Engineers
公開者 (ヨミ)	デンシ　ジョウホウ　ツウシン　ガッカイ
掲載誌名	IEICE TRANSACTIONS on Electronics
巻	99-C
号	4
開始ページ	431
終了ページ	439
刊行年月	2016-04-01
ISSN	09168524
ISSN	17451353
URL	http://hdl.handle.net/11094/55420
関連情報 (references)	https://search.ieice.org/
権利情報	Copyright © 2016 by The Institute of Electronics, Information and Communication Engineers
言語	英語

著者版フラグ	publisher
NII資源タイプ	学術雑誌論文
ローカル資源タイプ	学術雑誌論文
dcmi資源タイプ	text
DCTERMS.bibliographicCitation	IEICE TRANSACTIONS on Electronics.99-C(4) P.431-P.439
DC.title	A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices
DC.creator	Bae, Jungnam
	Radhapuram, Saichandrateja
	Jo, Ikkyun
	Wang, Weimin
	Kihara, Takao
	Matsuoka, Toshimasa
DC.publisher	電子情報通信学会
DC.language" scheme="DCTERMS.RFC1766	英語
DCTERMS.issued" scheme="DCTERMS.W3CDTF	2016-04-01
DC.identifier" scheme="DCTERMS.URI	http://hdl.handle.net/11094/55420
DC.subject	all-digital phase-locked loop
	controller
	digitally-controlled oscillator
	phase interpolator
	CMOS
	MICS
DCTERMS.abstract	A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band was designed in this study. In the proposed design, controller-based loop topology is used to control the phase and frequency to ensure the reliable handling of the ADPLL output signal. A digitally-controlled oscillator with a delta-sigma modulator was employed to achieve high frequency resolution. The phase error was reduced by a phase selector with a 64-phase signal from the phase interpolator. Fabricated using a 130-nm CMOS process, the ADPLL has an active area of 0.64 mm^2, consumes 840 µW from a 0.7-V supply voltage, and has a settling time of 80 µs. The phase noise was measured to be -114 dBc/Hz at an offset frequency of 200 kHz.
DC.rights	Copyright © 2016 by The Institute of Electronics, Information and Communication Engineers
citation_title	A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices
citation_author	Bae, Jungnam
	Radhapuram, Saichandrateja
	Jo, Ikkyun
	Wang, Weimin
	Kihara, Takao
	Matsuoka, Toshimasa
citation_publisher	電子情報通信学会
citation_language	英語
citation_date	2016-04-01
citation_journal_title	IEICE TRANSACTIONS on Electronics
citation_volume	99-C
citation_issue	4
citation_firstpage	431
citation_lastpage	439
citation_issn	09168524
citation_issn	17451353
citation_public_url	http://hdl.handle.net/11094/55420
citation_keywords	all-digital phase-locked loop
	controller
	digitally-controlled oscillator
	phase interpolator
	CMOS
	MICS

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