A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION

Cui, Ji; Tani, Sadahiro; Ohara, Kenji; Hirai, Yusaku; Matsuoka, Toshimasa

doi:https://doi.org/10.17654/fjecjun2015_105_115

A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION

Cui, Ji; Tani, Sadahiro; Ohara, Kenji et al.

Far East Journal of Electronics and Communications, 2015, 14(2), 105-115

Number of Access:736（2025-08-14 05:00 Counts）

Identifier to cite or link to this item: https://hdl.handle.net/11094/51765

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Title	A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION
Creator	CreatorName Cui, Ji
	CreatorName Tani, Sadahiro
	CreatorName Ohara, Kenji
	CreatorName Hirai, Yusaku
	NRID 1000080324820 1000080324820 ORCID 0000-0003-3876-2679 0000-0003-3876-2679 researchmap permalink read0068628 read0068628 Scopus Author ID 7402741552 7402741552 CreatorName Matsuoka, Toshimasa
Subject	dynamic latched comparator
Subject	offset voltage cancellation
Abstract	This paper presents a novel dynamic latched comparator that uses a built-in offset-cancellation technique. The proposed offset-cancellation scheme does not require any extra amplifiers or digital-assistant cancellation. Combining a conventional dynamic latched comparator with a one-stage amplifier benefits from not only an enhancement in comparator gain but also a reduction in power consumption. The Monte-Carlo simulation results, which were derived by using a 130‑nm CMOS process, show that the comparator achieved a 3.8 mV equivalent input-referred offset voltage at a 10 MHz clock rate while dissipating 2.7 μW from a 1.2V supply.
Publisher	Pushpa Publishing House
Source Title	Far East Journal of Electronics and Communications
Volume (Issue)	14(2)
Page	105-115
Date of Issued	2015-06
Language	English
Handle URL	https://hdl.handle.net/11094/51765
PISSN	09737006
Relation.isIdenticalTo	DOI (Publisher Version) https://doi.org/10.17654/fjecjun2015_105_115
Access Rights	open access
CopyRight	© 2015 Pushpa Publishing House
oaire:version	Version of Record
Category	学術雑誌論文 Journal Article

Resource Type	journal article
Local Type	Journal Article
DCMI Type	Text
DCTERMS.bibliographicCitation	Far East Journal of Electronics and Communications. 2015, 14(2), p. 105-115
DC.title	A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION
DC.creator	Cui, Ji
	Tani, Sadahiro
	Ohara, Kenji
	Hirai, Yusaku
	Matsuoka, Toshimasa
DC.publisher	Pushpa Publishing House
DC.language' scheme='DCTERMS.RFC1766	English
DC.type' scheme='DCTERMS.DCMIType	Text
DCTERMS.issued' scheme='DCTERMS.W3CDTF	2015-06
DC.identifier	https://doi.org/10.17654/fjecjun2015_105_115
DC.subject	dynamic latched comparator
DC.subject	offset voltage cancellation
DCTERMS.abstract	This paper presents a novel dynamic latched comparator that uses a built-in offset-cancellation technique. The proposed offset-cancellation scheme does not require any extra amplifiers or digital-assistant cancellation. Combining a conventional dynamic latched comparator with a one-stage amplifier benefits from not only an enhancement in comparator gain but also a reduction in power consumption. The Monte-Carlo simulation results, which were derived by using a 130‑nm CMOS process, show that the comparator achieved a 3.8 mV equivalent input-referred offset voltage at a 10 MHz clock rate while dissipating 2.7 μW from a 1.2V supply.
DC.rights	© 2015 Pushpa Publishing House
DC.format	51765
citation_title	A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION
citation_author	Cui, Ji
	Tani, Sadahiro
	Ohara, Kenji
	Hirai, Yusaku
	Matsuoka, Toshimasa
citation_publisher	Pushpa Publishing House
citation_language	English
citation_date	2015-06
citation_journal_title	Far East Journal of Electronics and Communications
citation_volume	14
citation_issue	2
citation_firstpage	105
citation_lastpage	115
citation_doi	https://doi.org/10.17654/fjecjun2015_105_115
citation_public_url	https://hdl.handle.net/11094/51765

A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION

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