Technical Note—Slowdown in the Energy Efficiency of Analog-to-Digital Converters and a Compressed-Sensing-Based Solution

Kanemoto, Daisuke

Number of Access:324（2025-11-25 03:09 Counts）

Identifier to cite or link to this item: https://doi.org/10.18910/101986

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Title
Technical Note—Slowdown in the Energy Efficiency of Analog-to-Digital Converters and a Compressed-Sensing-Based Solution
Creator
NRID
1000090603332 1000090603332
ORCID
0009-0002-7564-6351 0009-0002-7564-6351
researchmap permalink
dkanemoto dkanemoto
Scopus Author ID
6504308983 6504308983
CreatorName
Kanemoto, Daisuke
Subject
Analog-to-digital converter
ADC
compressed sensing
CS
energy efficiency
figure-of-merit
FoM
Abstract
Power consumption remains a critical bottleneck in the design of sensor systems. To investigate power consumption problems in sensor circuits, we surveyed the latest developments in analog-to-digital converter (ADC) integrated circuits, which are indispensable components of sensor front ends. An evaluation based on the Walden figure-of-merit, using data from ADCs presented at the International Solid-State Circuits Conference, revealed a slowdown in the energy-efficiency improvement of state-of-the-art ADCs. To overcome this limitation, we are developing a compressed-sensing-based solution: a lowpower sensing approach that combines random undersampling with compressed-sensing reconstruction. A prototype wireless electroencephalogram system implemented on a general-purpose microcontroller reduces both sampling activity and radio duty cycle, achieving continuous operation at 72 μWwhile maintaining signal fidelity. These efforts are expected to pave the way for next-generation ultralow-power and energy-harvesting sensor networks.
Publisher
Kanemoto, Daisuke
Language
English
Handle URL
https://hdl.handle.net/11094/101986
DOI
https://doi.org/10.18910/101986
Access Rights
open access
oaire:version
Version of Record
Category
ディスカッション／ワーキング・ペーパー DP/WP