Identifier to cite or link to this item: https://hdl.handle.net/11094/27256

Link to primary information 

File	Format	Terms of use	Size	Views	Date.Available	Description	information
IEICE_E84-D_5_635	pdf	None	1.93 MB	145	2014.04.03

Item Information

Output File Export EndNote Basic Export Mendeley

Title	Error Models and Fault-Secure Scheduling in Multiprocessor Systems
Creator	NRID 1000080305309 1000080305309 CreatorName Hashimoto, Koji
	NRID 1000030283740 1000030283740 ORCID 0000-0002-3329-9235 0000-0002-3329-9235 researchmap permalink tatsuhirotsuchiya72 tatsuhirotsuchiya72 Scopus Author ID 7403030658 7403030658 CreatorName Tsuchiya, Tatsuhiro
	NRID 1000050093745 1000050093745 CreatorName Kikuno, Tohru
Subject	multiprocessors
	fault-secure scheduling
	task graphs
	error models
	tests
Publisher	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
Source Title	IEICE transactions on information and systems
Volume (Issue)	E84-D(5)
Page	635-650
Date of Issued	2001-05-01
Language	English
Handle URL	https://hdl.handle.net/11094/27256
PISSN	09168532
NCID	AA10826272
Relation.references	URI http://search.ieice.org/
Access Rights	open access
CopyRight	Copyright © 2001 The Institute of Electronics, Information and Communication Engineers
oaire:version	Version of Record
Category	学術雑誌論文 Journal Article

Back to Home