High Speed and Noise Tolerant Parallel Bus Interface for VLSI Systems Using Multi Bit Code Division Multiple Access

Shimizu, Shinsaku; Matsuoka, Toshimasa; Taniguchi, Kenji

IEICE Transactions on Electronics, 2004, E87-C(11), 1923-1927

Number of Access:317（2025-08-15 22:51 Counts）

Identifier to cite or link to this item: https://hdl.handle.net/11094/51684

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Title
High Speed and Noise Tolerant Parallel Bus Interface for VLSI Systems Using Multi Bit Code Division Multiple Access
Creator
CreatorName
Shimizu, Shinsaku
NRID
1000080324820 1000080324820
ORCID
0000-0003-3876-2679 0000-0003-3876-2679
researchmap permalink
read0068628 read0068628
Scopus Author ID
7402741552 7402741552
CreatorName
Matsuoka, Toshimasa
NRID
1000020192180 1000020192180
CreatorName
Taniguchi, Kenji
Subject
parallel-CDMA interface
noise tolerance
multi-bit transmission
Abstract
An efficient data transmission interface for VLSI systems, Multi-Bit Parallel Code Division Multiple Access (MB/P-CDMA) interface, has been designed with 0.35 µm CMOS technology. The proposed interface achieves 1.12 Gb/s data rate (80 MHz, 8 bit bus) using multi-bit transmission at each clock per transmitter. The proposed CDMA interface ensures higher speed operation than conventional interface even in noisy environments. Each of the transmitters and receivers occupies the die area of 290 × 360 µm2 and 240 × 280 µm2, respectively.
Publisher
電子情報通信学会
The Institute of Electronics, Information and Communication Engineers
デンシ　ジョウホウ　ツウシン　ガッカイ
Source Title
IEICE Transactions on Electronics
Volume (Issue)
E87-C(11)
Page
1923-1927
Date of Issued
2004-11
Language
English
Handle URL
https://hdl.handle.net/11094/51684
PISSN
09168516
NCID
AA10826261
Relation.references
URI
https://search.ieice.org/
Access Rights
open access
CopyRight
copyright©2004 IEICE
oaire:version
Version of Record
Category
学術雑誌論文 Journal Article