Threshold Voltage Mismatch of FD-SOI MOSFETs

Shimizu, Yoshiyuki; Matsuoka, Toshimasa; Taniguchi, Kenji

IEICE Transactions on Electronics, 2004, E87-C(6), 1013-1014

Number of Access:943（2025-08-14 01:38 Counts）

Identifier to cite or link to this item: https://hdl.handle.net/11094/51685

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Title
Threshold Voltage Mismatch of FD-SOI MOSFETs
Creator
CreatorName
Shimizu, Yoshiyuki
NRID
1000080324820 1000080324820
ORCID
0000-0003-3876-2679 0000-0003-3876-2679
researchmap permalink
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Scopus Author ID
7402741552 7402741552
CreatorName
Matsuoka, Toshimasa
NRID
1000020192180 1000020192180
CreatorName
Taniguchi, Kenji
Subject
threshold voltage
FD-SOI
floating body effect
DIBL
Abstract
The threshold voltage mismatch of FD (Fully depleted) SOI (Silicon on insulator) devices have been studied. Floating body MOSFETs operating at high drain voltage show a large mismatch in the threshold voltage compared with body-tied MOSFETs. Those experimental data under different drain voltages indicate that both floating body effect and DIBL (Drain induced barrier lowering) are involved in the threshold voltage mismatch of floating body MOSFETs.
Publisher
電子情報通信学会
The Institute of Electronics, Information and Communication Engineers
デンシ　ジョウホウ　ツウシン　ガッカイ
Source Title
IEICE Transactions on Electronics
Volume (Issue)
E87-C(6)
Page
1013-1014
Date of Issued
2004-06
Language
English
Handle URL
https://hdl.handle.net/11094/51685
PISSN
09168516
NCID
AA10826261
Relation.references
URI
https://search.ieice.org/
Access Rights
open access
CopyRight
copyright©2004 IEICE
oaire:version
Version of Record
Category
学術雑誌論文 Journal Article