Design of a 500-MS/s stochastic signal detection circuit using a non-linearity reduction technique in a 65-nm CMOS process

Ham, Hyunju; Matsuoka, Toshimasa; Wang, Jun et al.

IEICE Electronics Express, 2011, 8(6), 353-359

Number of Access:331（2025-08-14 16:32 Counts）

Identifier to cite or link to this item: https://hdl.handle.net/11094/51716

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Title
Design of a 500-MS/s stochastic signal detection circuit using a non-linearity reduction technique in a 65-nm CMOS process
Creator
CreatorName
Ham, Hyunju
NRID
1000080324820 1000080324820
ORCID
0000-0003-3876-2679 0000-0003-3876-2679
researchmap permalink
read0068628 read0068628
Scopus Author ID
7402741552 7402741552
CreatorName
Matsuoka, Toshimasa
NRID
1000030543532 1000030543532
CreatorName
Wang, Jun
NRID
1000020192180 1000020192180
CreatorName
Taniguchi, Kenji
Subject
signal detection
comparator
mismatch
CMOS
Abstract
A stochastic signal detection circuit that uses a non-linearity reduction technique is designed using a 65-nm CMOS process. The fabricated chip demonstrates the feasibility of stochastic signal detection at 500MS/s.
Publisher
電子情報通信学会
The Institute of Electronics, Information and Communication Engineers
デンシ　ジョウホウ　ツウシン　ガッカイ
Source Title
IEICE Electronics Express
Volume (Issue)
8(6)
Page
353-359
Date of Issued
2011-03
Language
English
Handle URL
https://hdl.handle.net/11094/51716
eISSN
13492543
Relation.isIdenticalTo
DOI (Publisher Version)
https://doi.org/10.1587/elex.8.353
Access Rights
open access
CopyRight
copyright©2011 IEICE
oaire:version
Version of Record
Category
学術雑誌論文 Journal Article