CMOS Front-end Circuits of Dual-band GPS Receiver

Utsurogi, Yoshihiro; Haruoka, Masaki; Matsuoka, Toshimasa et al.

IEICE Transactions on Electronics, 2005, E88-C(6), 1275-1279

Number of Access:485（2025-09-22 03:33 Counts）

Identifier to cite or link to this item: https://hdl.handle.net/11094/51717

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Title
CMOS Front-end Circuits of Dual-band GPS Receiver
Creator
CreatorName
Utsurogi, Yoshihiro
CreatorName
Haruoka, Masaki
NRID
1000080324820 1000080324820
ORCID
0000-0003-3876-2679 0000-0003-3876-2679
researchmap permalink
read0068628 read0068628
Scopus Author ID
7402741552 7402741552
CreatorName
Matsuoka, Toshimasa
NRID
1000020192180 1000020192180
CreatorName
Taniguchi, Kenji
Subject
dual-band GPS receiver
L1/L2
LNA
image-reject mixer
image-rejection ratio (IMRR)
Abstract
A RF front-end chip for a dual-band Global Positioning System (GPS) receiver for L1 and L2 bands is designed using 0.25 µm CMOS technology. All function blocks of the GPS front-end are integrated onto one chip. The low noise amplifier has input matching over a wide frequency range to handle the L1 and L2 bands. This receiver uses a dual-band image-reject mixer with the quadrature mixer sharing a transconductor stage. This configuration enables the RF blocks to be shared with the L1 and L2 bands. The receiver has a chip area of 3.16 mm × 3.16 mm, and consumes 35 mA at 2.5 V.
Publisher
電子情報通信学会
The Institute of Electronics, Information and Communication Engineers
デンシ　ジョウホウ　ツウシン　ガッカイ
Source Title
IEICE Transactions on Electronics
Volume (Issue)
E88-C(6)
Page
1275-1279
Date of Issued
2005-06
Language
English
Handle URL
https://hdl.handle.net/11094/51717
PISSN
09168516
NCID
AA10826261
Relation.references
URI
https://search.ieice.org/
Access Rights
open access
CopyRight
copyright©2005 IEICE
oaire:version
Version of Record
Category
学術雑誌論文 Journal Article