A low-power CMOS programmable frequency divider with novel retiming scheme

Radhapuram, Saichandrateja; Bae, Jungnam; Jo, Ikkyun; Kihara, Takao; Matsuoka, Toshimasa

doi:https://doi.org/10.1587/elex.12.20141233

A low-power CMOS programmable frequency divider with novel retiming scheme

Radhapuram, Saichandrateja; Bae, Jungnam; Jo, Ikkyun et al.

IEICE Electronics Express, 2015, 12(6), 20141233

Number of Access:347（2025-05-03 12:46 Counts）

Identifier to cite or link to this item: https://hdl.handle.net/11094/51718

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Title	A low-power CMOS programmable frequency divider with novel retiming scheme
Creator	CreatorName Radhapuram, Saichandrateja
	CreatorName Bae, Jungnam
	CreatorName Jo, Ikkyun
	CreatorName Kihara, Takao
	NRID 1000080324820 1000080324820 ORCID 0000-0003-3876-2679 0000-0003-3876-2679 researchmap permalink read0068628 read0068628 Scopus Author ID 7402741552 7402741552 CreatorName Matsuoka, Toshimasa
Subject	pulse-swallow
	retiming
	SR latch
	modulus control
	CMOS
Abstract	We propose a novel pulse-swallow programmable frequency divider with a D flip-flop for retiming. The proposed scheme reduces the critical delay path of the modulus control (MC) signal extending the MC timing margin. This enables the high-speed operation of the divider. Moreover, unlike the conventional retiming structure, the MC signal is set and reset by a single signal triggered reset circuitry to eliminate the unwanted division ratio offset and the possible malfunction of set-reset (SR) latch. Simulation results show that the proposed divider designed in 130-nm CMOS technology consumes 53 µW at 1-GHz operation frequency from a 0.7-V supply voltage. The proposed divider achieves the lowest power consumption among the previously reported dividers at GHz operations.
Publisher	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
Source Title	IEICE Electronics Express
Volume (Issue)	12(6)
Page	20141233
Date of Issued	2015-03
Language	English
Handle URL	https://hdl.handle.net/11094/51718
eISSN	13492543
Relation.isIdenticalTo	DOI (Publisher Version) https://doi.org/10.1587/elex.12.20141233
Access Rights	open access
CopyRight	copyright©2015 IEICE
oaire:version	Version of Record
Category	学術雑誌論文 Journal Article

Resource Type	journal article
Local Type	Journal Article
DCMI Type	Text
DCTERMS.bibliographicCitation	IEICE Electronics Express. 2015, 12(6), p. 20141233
DC.title	A low-power CMOS programmable frequency divider with novel retiming scheme
DC.creator	Radhapuram, Saichandrateja
	Bae, Jungnam
	Jo, Ikkyun
	Kihara, Takao
	Matsuoka, Toshimasa
DC.publisher	電子情報通信学会
	The Institute of Electronics, Information and Communication Engineers
	デンシ　ジョウホウ　ツウシン　ガッカイ
DC.language' scheme='DCTERMS.RFC1766	English
DC.type' scheme='DCTERMS.DCMIType	Text
DCTERMS.issued' scheme='DCTERMS.W3CDTF	2015-03
DC.identifier	https://doi.org/10.1587/elex.12.20141233
DC.subject	pulse-swallow
	retiming
	SR latch
	modulus control
	CMOS
DCTERMS.abstract	We propose a novel pulse-swallow programmable frequency divider with a D flip-flop for retiming. The proposed scheme reduces the critical delay path of the modulus control (MC) signal extending the MC timing margin. This enables the high-speed operation of the divider. Moreover, unlike the conventional retiming structure, the MC signal is set and reset by a single signal triggered reset circuitry to eliminate the unwanted division ratio offset and the possible malfunction of set-reset (SR) latch. Simulation results show that the proposed divider designed in 130-nm CMOS technology consumes 53 µW at 1-GHz operation frequency from a 0.7-V supply voltage. The proposed divider achieves the lowest power consumption among the previously reported dividers at GHz operations.
DC.rights	copyright©2015 IEICE
DC.format	51718
citation_title	A low-power CMOS programmable frequency divider with novel retiming scheme
citation_author	Radhapuram, Saichandrateja
	Bae, Jungnam
	Jo, Ikkyun
	Kihara, Takao
	Matsuoka, Toshimasa
citation_publisher	電子情報通信学会
citation_language	English
citation_date	2015-03
citation_journal_title	IEICE Electronics Express
citation_volume	12
citation_issue	6
citation_firstpage	20141233
citation_doi	https://doi.org/10.1587/elex.12.20141233
citation_public_url	https://hdl.handle.net/11094/51718

A low-power CMOS programmable frequency divider with novel retiming scheme

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