A CMOS LOW-DROPOUT REGULATOR WITH A DYNAMIC-BIASED GAIN STAGE

Wang, Honglai; Dai, Yujie; Zhang, Xiaoxing et al.

Far East Journal of Electronics and Communications, 2012, 7(2), 67-81

Number of Access:332（2025-07-02 16:01 Counts）

Identifier to cite or link to this item: https://hdl.handle.net/11094/51735

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Title
A CMOS LOW-DROPOUT REGULATOR WITH A DYNAMIC-BIASED GAIN STAGE
Creator
CreatorName
Wang, Honglai
CreatorName
Dai, Yujie
CreatorName
Zhang, Xiaoxing
CreatorName
Lv, Yingjie
NRID
1000080324820 1000080324820
ORCID
0000-0003-3876-2679 0000-0003-3876-2679
researchmap permalink
read0068628 read0068628
Scopus Author ID
7402741552 7402741552
CreatorName
Matsuoka, Toshimasa
NRID
1000030543532 1000030543532
CreatorName
Wang, Jun
NRID
1000020192180 1000020192180
CreatorName
Taniguchi, Kenji
Subject
CMOS
frequency compensation
low-dropout(LDO) regulator
dynamic-biased gain stage
Abstract
This paper presents a CMOS low-dropout (LDO) regulation with a dynamic-biased gain stage. The dynamic-biased gain stage which has the dynamic adjustable output resistance, current and gain is designed as a second stage driving the power transistor. A LDO regulator with the proposed gain stage has been implemented in a 0.18mm standard CMOS process and occupies 0.11mm2 chip area. The experimental results show that the proposed LDO regulator can be stable without any additional on-chip compensation capacitors or complex circuit. The LDO regulator provides a full load transient response of settling time less than 15ms with a 2.2mF load capacitor and the voltage variation is less than 40mV. Furthermore, the load regulation and line regulation are 321mV/mA and 1.8mV/V, respectively.
Publisher
Pushpa Publishing House
Source Title
Far East Journal of Electronics and Communications
Volume (Issue)
7(2)
Page
67-81
Date of Issued
2012-04
Language
English
Handle URL
https://hdl.handle.net/11094/51735
PISSN
09737006
Access Rights
open access
CopyRight
© 2011 Pushpa Publishing House
oaire:version
Version of Record
Category
学術雑誌論文 Journal Article