ANALYSIS OF A CONTROLLER-BASED ALL-DIGITAL PHASE-LOCKED LOOP

Radhapuram, Saichandrateja; Bae, Jungnam; Jo, Ikkyun et al.

Far East Journal of Electronics and Communications, 2015, 15(1), 57-73

Number of Access:559（2025-06-06 19:11 Counts）

Identifier to cite or link to this item: https://hdl.handle.net/11094/52099

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Title
ANALYSIS OF A CONTROLLER-BASED ALL-DIGITAL PHASE-LOCKED LOOP
Creator
CreatorName
Radhapuram, Saichandrateja
CreatorName
Bae, Jungnam
CreatorName
Jo, Ikkyun
CreatorName
Wang, Weimin
NRID
1000080324820 1000080324820
ORCID
0000-0003-3876-2679 0000-0003-3876-2679
researchmap permalink
read0068628 read0068628
Scopus Author ID
7402741552 7402741552
CreatorName
Matsuoka, Toshimasa
Subject
all-digital phase-locked loop
phase interpolator
z-domain
s-domain
steady-state error
Abstract
A design procedure of an all-digital phase-locked loop (ADPLL) based on phase selection mechanism with loop stability independent of process, supply voltage and temperature is presented. A poly-phase filter and a phase interpolator are used to generate multiple phases to reduce the phase error. The modeling of proposed ADPLL structure is extensively investigated and mathematically described. For a phase and a frequency step input change, the closed-loop system of the proposed ADPLL eliminates phase error. Time-domain response of the behavioral-level simulation of the proposed structure on 130-nm CMOS technology with 0.7V supply voltage reveals the presented analytical model.
Publisher
Pushpa Publishing House
Source Title
Far East Journal of Electronics and Communications
Volume (Issue)
15(1)
Page
57-73
Date of Issued
2015-09
Language
English
Handle URL
https://hdl.handle.net/11094/52099
PISSN
09737006
Relation.isIdenticalTo
DOI (Publisher Version)
https://doi.org/10.17654/fjecsep2015_057_073
Access Rights
open access
CopyRight
© 2015 Pushpa Publishing House
oaire:version
Version of Record
Category
学術雑誌論文 Journal Article