An offset distribution modification technique of stochastic flash ADC

Asano, Tomohiro; Hirai, Yusaku; Tani, Sadahiro et al.

IEICE Electronics Express, 2016, 13(6), 1-10

Number of Access:838（2025-08-14 01:17 Counts）

Identifier to cite or link to this item: https://hdl.handle.net/11094/55419

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Title
An offset distribution modification technique of stochastic flash ADC
Creator
CreatorName
Asano, Tomohiro
CreatorName
Hirai, Yusaku
CreatorName
Tani, Sadahiro
CreatorName
Yano, Shinya
CreatorName
Jo, Ikkyun
NRID
1000080324820 1000080324820
ORCID
0000-0003-3876-2679 0000-0003-3876-2679
researchmap permalink
read0068628 read0068628
Scopus Author ID
7402741552 7402741552
CreatorName
Matsuoka, Toshimasa
Subject
stochastic flash ADC
comparator
mismatch
CMOS
genetic　algorithm
Abstract
A new non-linearity reduction technique for stochastic flash ADC (SF-ADC) is proposed, focusing on distribution of comparator input-referred offsets. The SF-ADC test chip fabricated in a 130-nm CMOS process demonstrated the proposed technique can improve SNDR. In addition, the digital re-quantization also can improve the linearity more, where quantization level and fractional correction can be optimized using genetic algorithm.
Publisher
電子情報通信学会
The Institute of Electronics, Information and Communication Engineers
デンシ　ジョウホウ　ツウシン　ガッカイ
Source Title
IEICE Electronics Express
Volume (Issue)
13(6)
Page
1-10
Date of Issued
2016
Language
English
Handle URL
https://hdl.handle.net/11094/55419
eISSN
13492543
Relation.isIdenticalTo
DOI (Publisher Version)
https://doi.org/10.1587/elex.13.20160115
Access Rights
open access
CopyRight
Copyright © 2016 by The Institute of Electronics, Information and Communication Engineers
oaire:version
Version of Record
Category
学術雑誌論文 Journal Article