Excellent electrical properties of TiO2/HfSiO/SiO2 layered higher-k gate dielectrics with sub-1 nm equivalent oxide thickness

Arimura, Hiroaki; Kitano, Naomu; Naitou, Yuichi; Oku, Yudai; Minami, Takashi; Kosuda, Motomu; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

doi:https://doi.org/10.1063/1.2929680

Excellent electrical properties of TiO2/HfSiO/SiO2 layered higher-k gate dielectrics with sub-1 nm equivalent oxide thickness

Arimura, Hiroaki; Kitano, Naomu; Naitou, Yuichi et al.

Applied Physics Letters, 2008, 92(21), 212902

Number of Access:1,000（2025-08-19 00:56 Counts）

Identifier to cite or link to this item: https://hdl.handle.net/11094/85483

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Title	Excellent electrical properties of TiO2/HfSiO/SiO2 layered higher-k gate dielectrics with sub-1 nm equivalent oxide thickness
Creator	CreatorName Arimura, Hiroaki
	CreatorName Kitano, Naomu
	CreatorName Naitou, Yuichi
	CreatorName Oku, Yudai
	CreatorName Minami, Takashi
	CreatorName Kosuda, Motomu
	NRID 1000090452466 1000090452466 CreatorName Hosoi, Takuji
	NRID 1000090252600 1000090252600 ORCID 0000-0002-8859-7010 0000-0002-8859-7010 researchmap permalink read0042803 read0042803 Scopus Author ID 35510328800 35510328800 CreatorName Shimura, Takayoshi
	NRID 1000090379115 1000090379115 ORCID 0000-0002-7916-3093 0000-0002-7916-3093 researchmap permalink heijiw heijiw Scopus Author ID 7410305922 7410305922 CreatorName Watanabe, Heiji
Description	Hiroaki Arimura, Naomu Kitano, Yuichi Naitou, Yudai Oku, Takashi Minami, Motomu Kosuda, Takuji Hosoi, Takayoshi Shimura and Heiji Watanabe, "Excellent electrical properties TiO_2/HfSiO/SiO_2 of higher-k gate dielectrics with sub-1nm equivalent oxide thickness", Appl. Phys. Lett. 92, 212902 (2008) https://doi.org/10.1063/1.2929680
Abstract	Equivalent oxide thickness (EOT) scaling, as well as improved interface properties, of metal/higher- k gate stacks for the sub- 1 nm region was achieved using a TiO_2/HfSiO/SiO_2 layered dielectric structure. Ti diffusion into the bottom oxides was found to form electrical defects, which lead to an increase of leakage current, fixed charge, interface trap density (Dit), and reliability degradation of the gate stacks. By controlling Ti diffusion and terminating Ti-induced defects using forming gas annealing, we successfully obtained a superior interface property (Dit =9.9× 10^{10} eV^{-1} cm^{-2}) and reduced gate leakage (Jg =7.2× 10^{-2} A/cm^2) at the 0.71-nm -EOT region.
Publisher	American Institute of Physics
Source Title	Applied Physics Letters
Volume (Issue)	92(21)
Page	212902
Date of Issued	2008-05-26
Language	English
Handle URL	https://hdl.handle.net/11094/85483
PISSN	00036951
NCID	AA00543431
Relation.isIdenticalTo	DOI (Publisher Version) https://doi.org/10.1063/1.2929680
Access Rights	open access
CopyRight	This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. This article appeared in Appl. Phys. Lett. and may be found at https://doi.org/10.1063/1.2929680.
oaire:version	Version of Record
Category	学術雑誌論文 Journal Article

Resource Type	journal article
Local Type	Journal Article
DCMI Type	Text
DCTERMS.bibliographicCitation	Applied Physics Letters. 2008, 92(21), p. 212902
DC.title	Excellent electrical properties of TiO2/HfSiO/SiO2 layered higher-k gate dielectrics with sub-1 nm equivalent oxide thickness
DC.creator	Arimura, Hiroaki
	Kitano, Naomu
	Naitou, Yuichi
	Oku, Yudai
	Minami, Takashi
	Kosuda, Motomu
	Hosoi, Takuji
	Shimura, Takayoshi
	Watanabe, Heiji
DC.publisher	American Institute of Physics
DC.language' scheme='DCTERMS.RFC1766	English
DC.type' scheme='DCTERMS.DCMIType	Text
DCTERMS.issued' scheme='DCTERMS.W3CDTF	2008-05-26
DC.identifier	https://doi.org/10.1063/1.2929680
DC.description	Hiroaki Arimura, Naomu Kitano, Yuichi Naitou, Yudai Oku, Takashi Minami, Motomu Kosuda, Takuji Hosoi, Takayoshi Shimura and Heiji Watanabe, "Excellent electrical properties TiO_2/HfSiO/SiO_2 of higher-k gate dielectrics with sub-1nm equivalent oxide thickness", Appl. Phys. Lett. 92, 212902 (2008) https://doi.org/10.1063/1.2929680
DCTERMS.abstract	Equivalent oxide thickness (EOT) scaling, as well as improved interface properties, of metal/higher- k gate stacks for the sub- 1 nm region was achieved using a TiO_2/HfSiO/SiO_2 layered dielectric structure. Ti diffusion into the bottom oxides was found to form electrical defects, which lead to an increase of leakage current, fixed charge, interface trap density (Dit), and reliability degradation of the gate stacks. By controlling Ti diffusion and terminating Ti-induced defects using forming gas annealing, we successfully obtained a superior interface property (Dit =9.9× 10^{10} eV^{-1} cm^{-2}) and reduced gate leakage (Jg =7.2× 10^{-2} A/cm^2) at the 0.71-nm -EOT region.
DC.rights	This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. This article appeared in Appl. Phys. Lett. and may be found at https://doi.org/10.1063/1.2929680.
DC.format	85483
citation_title	Excellent electrical properties of TiO2/HfSiO/SiO2 layered higher-k gate dielectrics with sub-1 nm equivalent oxide thickness
citation_author	Arimura, Hiroaki
	Kitano, Naomu
	Naitou, Yuichi
	Oku, Yudai
	Minami, Takashi
	Kosuda, Motomu
	Hosoi, Takuji
	Shimura, Takayoshi
	Watanabe, Heiji
citation_publisher	American Institute of Physics
citation_language	English
citation_date	2008-05-26
citation_journal_title	Applied Physics Letters
citation_volume	92
citation_issue	21
citation_firstpage	212902
citation_doi	https://doi.org/10.1063/1.2929680
citation_public_url	https://hdl.handle.net/11094/85483

Excellent electrical properties of TiO2/HfSiO/SiO2 layered higher-k gate dielectrics with sub-1 nm equivalent oxide thickness

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