GaOₓ interlayer-originated hole traps in SiO₂/p-GaN MOS structures and their suppression by low-temperature gate dielectric deposition

Hara, Masahiro; Kobayashi, Takuma; Nozaki, Mikito; Watanabe, Heiji

doi:https://doi.org/10.1063/5.0246368

GaOₓ interlayer-originated hole traps in SiO₂/p-GaN MOS structures and their suppression by low-temperature gate dielectric deposition

Hara, Masahiro; Kobayashi, Takuma; Nozaki, Mikito et al.

Applied Physics Letters, 2025, 126(2), 022113

Number of Access:631（2025-07-27 21:13 Counts）

Identifier to cite or link to this item: https://hdl.handle.net/11094/99613

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Title	GaOₓ interlayer-originated hole traps in SiO₂/p-GaN MOS structures and their suppression by low-temperature gate dielectric deposition
Creator	ORCID 0000-0001-9748-8011 0000-0001-9748-8011 researchmap permalink masahirohara masahirohara CreatorName Hara, Masahiro
	NRID 1000020827711 1000020827711 ORCID 0000-0002-2755-5079 0000-0002-2755-5079 researchmap permalink takumakobayashi takumakobayashi Scopus Author ID 57203742549 57203742549 CreatorName Kobayashi, Takuma
	NRID 1000090646217 1000090646217 ORCID 0009-0008-2368-1036 0009-0008-2368-1036 researchmap permalink n0z n0z CreatorName Nozaki, Mikito
	NRID 1000090379115 1000090379115 ORCID 0000-0002-7916-3093 0000-0002-7916-3093 researchmap permalink heijiw heijiw Scopus Author ID 7410305922 7410305922 CreatorName Watanabe, Heiji
Description	Hara Masahiro et al., Appl. Phys. Lett. 126, 0122113 (2025) https://doi.org/10.1063/5.0246368.
Abstract	In this study, we investigated the impact of SiO2 deposition temperature during plasma-enhanced chemical vapor deposition on the generation of fast hole traps, which cause surface potential pinning, in p-type GaN MOS structures. The thickness of a gallium oxide (GaOx) layer at the SiO2/GaN interface was estimated and correlated with the hole trap generation. The 200℃-deposited SiO2/GaN MOS structures exhibited a smaller amount of fast hole traps and a thinner GaOx interlayer than the 400℃-deposited samples. In the 200℃-deposited samples, annealing at a temperature below 600℃ did not lead to an increase in the fast hole trap and GaOx layer thickness, while the amount of fast traps significantly increased just after 800℃-annealing in O2 ambient, accompanied by the growth of the GaOx interlayer. These findings suggest that the major origin of fast hole traps in SiO2/GaN MOS structures is a thermally induced defect existing inside a GaOx interlayer and that the low-temperature SiO2 deposition is effective in reducing the fast traps.
Publisher	AIP Publishing
Source Title	Applied Physics Letters
Volume (Issue)	126(2)
Page	022113
Date of Issued	2025-01-15
Language	English
Handle URL	https://hdl.handle.net/11094/99613
PISSN	00036951
eISSN	10773118
Relation.isVersionOf	DOI (Publisher Version) https://doi.org/10.1063/5.0246368
Access Rights	open access
CopyRight	This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. This article appeared in Appl. Phys. Lett. 15 January 2025; 126 (2): 022113 and may be found at https://doi.org/10.1063/5.0246368.
oaire:version	Accepted Manuscript
Category	学術雑誌論文 Journal Article

Resource Type	journal article
Local Type	Journal Article
DCTERMS.bibliographicCitation	Applied Physics Letters. 2025, 126(2), p. 022113
DC.title	GaOₓ interlayer-originated hole traps in SiO₂/p-GaN MOS structures and their suppression by low-temperature gate dielectric deposition
DC.creator	Hara, Masahiro
	Kobayashi, Takuma
	Nozaki, Mikito
	Watanabe, Heiji
DC.publisher	AIP Publishing
DC.language' scheme='DCTERMS.RFC1766	English
DCTERMS.issued' scheme='DCTERMS.W3CDTF	2025-01-15
DC.identifier	https://doi.org/10.1063/5.0246368
DC.description	Hara Masahiro et al., Appl. Phys. Lett. 126, 0122113 (2025) https://doi.org/10.1063/5.0246368.
DCTERMS.abstract	In this study, we investigated the impact of SiO2 deposition temperature during plasma-enhanced chemical vapor deposition on the generation of fast hole traps, which cause surface potential pinning, in p-type GaN MOS structures. The thickness of a gallium oxide (GaOx) layer at the SiO2/GaN interface was estimated and correlated with the hole trap generation. The 200℃-deposited SiO2/GaN MOS structures exhibited a smaller amount of fast hole traps and a thinner GaOx interlayer than the 400℃-deposited samples. In the 200℃-deposited samples, annealing at a temperature below 600℃ did not lead to an increase in the fast hole trap and GaOx layer thickness, while the amount of fast traps significantly increased just after 800℃-annealing in O2 ambient, accompanied by the growth of the GaOx interlayer. These findings suggest that the major origin of fast hole traps in SiO2/GaN MOS structures is a thermally induced defect existing inside a GaOx interlayer and that the low-temperature SiO2 deposition is effective in reducing the fast traps.
DC.rights	This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. This article appeared in Appl. Phys. Lett. 15 January 2025; 126 (2): 022113 and may be found at https://doi.org/10.1063/5.0246368.
DC.format	99613
citation_title	GaOₓ interlayer-originated hole traps in SiO₂/p-GaN MOS structures and their suppression by low-temperature gate dielectric deposition
citation_author	Hara, Masahiro
	Kobayashi, Takuma
	Nozaki, Mikito
	Watanabe, Heiji
citation_publisher	AIP Publishing
citation_language	English
citation_date	2025-01-15
citation_journal_title	Applied Physics Letters
citation_volume	126
citation_issue	2
citation_firstpage	022113
citation_doi	https://doi.org/10.1063/5.0246368
citation_public_url	https://hdl.handle.net/11094/99613

GaOₓ interlayer-originated hole traps in SiO₂/p-GaN MOS structures and their suppression by low-temperature gate dielectric deposition

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